Although the single-cycle design is conceptually simple, it has several drawbacks. One of the most significant drawbacks is its inefficiency.
Figure 8.1a Single cycle implementation.
In a single-cycle design, the clock cycle must have the same length for every instruction, as it uses five functional units in series:
As a result, the clock cycle is too long for other instructions that require less processing time, and this leads to poor performance. For these reasons, modern CPUs use a multi-cycle design.
Figure 8.1b Multiple cycle implementation.
The idea is that each step in the execution will take 1 clock cycle.
The multicycle implementation allows a functional unit to be used more than once per instruction, as long as it is used on different clock cycles — thus reducing the amount of hardware required.
Figure 8.2 The multi-cycle datapath (Textbook implementation).
But, as we will see, it requires a more complex control unit because it needs to generate a different set of control signals for each cycle of the instruction execution.
Before going further, let’s draw out the multi-cycle datapath. This will be similar to the textbook implementation, but formatted a bit differently.