• Table of Contents

Defining the Control

In a multi-cycle implementation, generating control signals is more challenging than using an opcode input with simple high or low signals as in a single-cycle implementation. However, the datapath remains mostly the same, with additional checkpoints to save instruction progress.

Instruction Class

To better understand multi-cycle control signal generation, we can categorize MIPS instructions into four types.

Figure 9.1 Summary of the steps taken to execute any instruction class.

As you can see each category requires a different set of control signals to be generated.

1. R-Type: These instructions perform operations on registers and have a fixed format — add $s1, $s2, $s3.
2. Memory-Reference: These instructions access memory and may have a variable format depending on the addressing mode used — lw $t0, 100($s1) and sw $t0, 200($s2).
3. Branches: These instructions change the program counter (PC) to execute a different part of the code — beq $s1, $s2, Label.
4. Jumps: These instructions change the PC to an absolute address — jal Label.

Do note how the first two steps are pretty much identical.

Finite State Machine

The multicycle control can be thought of as a finite state machine (FSM), which consists of a set of states and transition rules between them.

Figure 9.2a Overview of the finite state machine.

Each bubble in the FSM diagram represents a state in the control sequence and each line connecting the bubbles represents a transition from one state to another.

• The reason for each transition is listed on the line and is explained on the connector.
• If there is no reason given for a transition, then it is automatic and moves to the next state.
• The transitions happen on the next clock edge.