<aside> <img src="/icons/map-pin_gray.svg" alt="/icons/map-pin_gray.svg" width="40px" /> Relevant Notes/Resources: 12 Analog-to-Digital Converter Registers (Page 4 - 5)

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• Question

a) Filling in the Blank

These pretty much just rely on your ability to read the appendix, as you will be given a list of settings and you would have to look at each register and set/clear the bits accordingly. There are some which are more obvious than others.

If not mentioned in the settings, check the value of that bit at reset ****— ****or just right all of them at 0, you at least got 50/50 chance of it being right. ****It may help, if we group together these settings with their respective register:

• ATD CTL2
  • fast ATD flag clear all enabled
  • external trigger mode disabled
  • disable sequence complete interrupt
• ATD CTL3
  • disable FIFO mode
• ATD CTL4
  • 8-bit resolution and 4 A/D clock periods of the second stage sample time
  • choose 1 MHz as the conversion frequency for the 24 MHz bus clock
• ATD CTL5
  • perform 4 A/D conversions of the signal on channel AN7 and stop
  • result is right justified and unsigned

Now let’s fill in the bits in the register.

1. ADPU = 1 : The ATD needs to be powered on to actual operate.
2. AFFC = 1 : To enable fast ATD flag clear all.
3. ETRIGLE = 0 and ETRIGP = 0 : Since it’s not specified, by default, it is set to 0.
4. ETRIGE = 0 : To disable external trigger mode.
5. ASCIE = 0 : To disable sequence complete interrupt.