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Section 1: Memory subsystem organization

The block diagram of the memory subsystem is shown below.

Before going over the question, let’s denote how these specifications translate to the block diagram.

Question 1.1

Estimate organization of the bus between cache controller (in the FPGA) and CPU:

1. Bus type (circle the correct variant):

   1. Serial synchronous
   2. Parallel synchronous
   3. Serial asynchronous
   4. Parallel asynchronous

2. Number of FPGA pins reserved for the CPU VM address lines = ________________

3. Number of FPGA pins reserved for the CPU Data lines = ________________

4. Circle control signals which must be used for CPU-to-Cache interface

   Control lines RAS CAS WE OE Clock

5. Calculate CPU Data Bus bandwidth = ________________

1. As you can see from the block diagram, it’s not serial since multiple lines. We will always use synchronous regardless, so it’ll always be parallel synchronous.

2. The number of FPGA pins reserved for the CPU VM address line is given by:

   $$ \log_2(4\;\text{G}) = \log_2(4 \times 2^{30}) = 32 $$

3. A data word is $4\;\text{B}$. The number of FPGA pins reserved for the CPU Data lines is given by:

   $$ 4\;\text{B} \Rightarrow 8 \times 4\;\text{bits} $$

4. The CPU-to-Cache interface uses WE and OE.

5. The CPU provides a bus clock frequency of $250\;\text{MHz}$, then

   $$ (250\times10^{6}\;\text{word/sec}) \times (4\;\text{B/word}) = 10^9\;\text{B/sec} $$

   or more simplified to in MB, which is divided by $2^{20}$:

   $$ 10^9\;\text{B/sec} \times \frac{1\;\text{KB}}{1024\;\text{B}} \times \frac{1\;\text{MB}}{1024\;\text{KB}} \approx 953.674\;\text{MB/sec} $$

Question 1.2

Estimate bus organization between the cache (in the FPGA) & Main memory (SDRAM):

1. Bus type (circle the correct variant):

   1. Serial synchronous
   2. Parallel synchronous
   3. Serial asynchronous
   4. Parallel asynchronous

2. Number of FPGA pins reserved for SDRAM address lines = ________________

3. Number of FPGA pins reserved for the Memory Data lines = ________________

4. Circle strobe &synchronization signals used for cache-to-SDRAM interface

   Control lines RAS CAS WE OE Clock

5. Calculate DDR SDRAM Data Bus bandwidth = ________________

1. Likewise, this is also parallel synchronous.

2. The number of FPGA pins reserved for SDRAM address line is given by:

   $$ \log_2(1\;\text{G})\div 2 = \log_2(1 \times 2^{30}) \div 2 = 15 $$

   Recall that SDRAM allows DDR access, so we divide by two.