The following partial specifications are given:

Question 1.1

To determine the miss penalty (time to replace the block in cache) for the worst-case scenario (D-bit for the block to be replaced always = $1$) calculate the following:

• Bus clock period
• Bus transfer time
• Block replacement time (if D-bit = 1)
• Miss penalty

This question is just a matter of knowing the formula.

• The bus clock period is the reciprocal of the bus clock frequency.

  $$ t_{\text{bus}} = \frac{1}{f_{\text{bus}}} = \frac{1}{133.33 \times 10^6\;\text{Hz}} \approx 7.5 \times 10^{-9}\;\text{s} \text{ or } 7.5\;\text{ns} $$

  Make sure you know the SI conversions, most notably for $\text{mega (M)}$ and $\text{nano (n)}$, as these will be those you’ll see the most for these tests.

• The block transfer time is the product of the number of words being transferred and the bus clock period.

  $$ T_{\text{bt}} = \text{\# of words} \times t_{\text{bus}} = 32\;\text{words} \times 7.5\;\text{ns} = 240\;\text{ns} $$

• The block replacement time is given by the following formula.

  $$ T_{\text{br}} = (T_{\text{addr}} + T_{\text{bt}}) (L + BRR) $$

  Since $L$ is not given, we assume it’s $100\%$. It also mentions “if D-bit = 1”, which is the dirty-bit approach, so $BRR = 100\%$.

  $$ T_{\text{br}} = (80\;\text{ns} + 240\;\text{ns}) (1 + 1) = 640\;\text{ns} $$

• The miss penalty is the summation of the block replacement time and cache hit.

  $$ T_{\text{miss}} = T_{\text{br}} + T_{\text{hit}} = 640\;\text{ns} + 10\;\text{ns} = 650\;\text{ns} $$

Question 1.2 Determine the miss penalty if main memory is based on DDR-SDRAM with the same system parameters as in previous case (according to the above specification).

Whenever you see DDR-SDRAM, just know that you have to divide the block transfer time by two.

$$ T_{\text{bt}} = \frac{\text{\# of words} \times t_{\text{bus}}}{2} = \frac{240\;\text{ns}}{2} = 120\;\text{ns} $$

This is because it allows two data-words during one clock cycle period, so the block transfer gets cut in half. The rest of the formula remains the same.

$$ T_{\text{miss}} = T_{\text{br}} = (80\;\text{ns} + 120\;\text{ns}) (2) + 10\;\text{ns} = 410\;\text{ns} $$

The system with DDR-SDRAM main memory has a miss penalty of $410\;\text{ns}$.

Question 1.3 Taking in account that average access time for the cache is equal to: Hit rate $\times$ Hit time + Miss rate $\times$ Miss penalty. Find the best variant of systems organization (with minimum average data access time) out of the following options:

1. Block size = $32$ words and Hit rate = $98\%$ & SDRAM based main memory
2. Block size = $16$ words and Hit rate = $96\%$ & SDRAM based main memory
3. Block size = $32$ words and Hit rate = $98\%$ & DDR-SDRAM based main memory
4. Block size = $16$ words and Hit rate = $96\%$ & DDR-SDRAM based main memory

Calculate the value for the average data access time for each option. Fill in the Table 1.1 and select the best variant with $\min\{T_{\text{av}}\}$.

For this question, we are already given the formula for average access time, which is: