• Table of Contents

Overview

As a way of introducing the concept of pipelining, a common analogy often used is one involving laundry. The analogy goes as follows:

Imagine you have a pile of dirty laundry that needs to be washed, dried, and folded.

• Sequential approach: Wash all the clothes, then dry them all, and finally fold them all, where each step must be completed before moving on to the next.
• Pipelined approach: Start washing the first load of clothes, while at the same time drying the second load, and folding the third load.

The pipelined approach takes much less time, as the main idea is that as long as we have separate resources for each stage, we can pipeline the tasks.

Figure 10.1 The laundry analogy for pipelining.

The same principles apply to processors where we pipeline instruction execution.

Single-Cycle, Multi-Cycle, and Pipeline

To get a better understanding, let’s compare all three architectures.

• Single-cycle CPU design executes each instruction in a single clock cycle. There’s no module reuse
• On the other hand, multi-cycle CPU design allows instructions to be executed in short clock cycles. There’s module reuse.

Now, compared to pipelining:

• Pipelined approach is a form of multi-cycle CPU design. As such, each instruction is divided into stages and executed short clock cycles.
• However, the reuse of modules is limited or even non-existent for the same instruction. We will expand more on this when we start to cover the hazards.

The idea is that if we apply pipelining to the multi-cycle CPU, after executing a few instructions, we can complete one instruction at a faster clock rate. This is illustrated in Figure 10.2.

Figure 10.2 Comparing clock cycle of each architecture.

The idea is that pipelining improves performance by increasing instruction throughput, as opposed to decreasing the execution time of an individual instruction.